1. Field of the Invention
This invention relates to a packaging structure in which a semiconductor device such as a memory or the like is used, and particularly to a stacked module formed by stacking semiconductor devices and connecting them and substrates used for the stacked module, in which a semiconductor device is mounted on the surface thereof, to be stacked.
2. Description of the Related Art
A known packaging method for a semiconductor device is that a semiconductor device is mounted on a substrate, the substrates are stacked in plural layers to construct a stacked module, and the module is mounted on a motherboard. This packaging for a semiconductor device by the stacked module is effective for reducing the packaging area.
The stacked module using a substrate is effectively utilized for packaging a semiconductor chip such as a semiconductor memory or the like. For example, the case of packaging dynamic RAMs (DRAM) 80, 81 of a memory circuit shown in FIG. 10 will be described. In FIG. 10, the external terminals of the DRAM 80, 81 are all shared except RAS (Row Address Strobe). The terminals 82, 83 connected to RAS are separately used for chip select. Chip select may be performed not by RAS, but by CAS (Column Address Strobe).
In FIG. 10, terminals other than a chip select terminal for determining which DRAMs 80, 81 is operated are shared, thus in the case of wiring packaging, substrates on which DRAMs are mounted can be stacked.
The stacked module is, for example, as described in Japan Patent Laid-Open No. 8-236694, such that a plurality of substrates (carrier) where a semiconductor chip (LSI chip) is mounted facedown are stacked and connection between the substrates is performed by metallic pins or conductive bumps.
FIG. 11 is a perspective view showing this type of a stacked module using conductive bumps. The stacked module of FIG. 11 is equivalent to a memory circuit of FIG. 10. In FIG. 11, semiconductor chips 3, 4 are respectively chips of DRAMs 80, 81 of FIG. 10.
The semiconductor chips 3, 4 are mounted facedown on substrates 100, 101. The matrix of the substrates 100, 101 is formed by an insulator such as ceramics, glass or the like. A conductive bump 5 is mounted on each electrode pad of the substrate 100, a conductive bump 6 is mounted on each electrode pad of the substrate 101, and the respective electrode pads are wired to terminals (not shown) of the semiconductor chips 3, 4. Connection between the substrates 100, 101 is performed through the conductive bumps 6. The conductive bumps 5 are served as external terminals at the time of connecting the stacked module of FIG. 11 facedown to a motherboard not shown.
FIG. 12A shows the upper substrate 100 where the semiconductor chip 3 is mounted, FIG. 12B shows the lower substrate 101 where the semiconductor chip 4 is mounted, and they are plan views respectively showing the condition before the conductive bumps 5, 6 are mounted.
Electrode pads 111 to 134 connected to the terminal (not shown) of the semiconductor device 3, on which the conductive bumps 5 are mounted, through hole electrode pads B111 to B134 connected to the electrode pads 111 to 134, and wirings for connecting the respective through hole electrode pads and the terminals of the semiconductor device 3 to each other are formed on the surface of the substrate 100.
On the other hand, electrode pads 141 to 164 connected to the terminals (not shown) of the semiconductor device 4, on which the conductive bumps 6 of FIG. 11 are mounted, through-hole electrode pads C111 to C134 connected to the electrode pads 141 to 164, and wiring for connecting the respective through-hole electrode pads and the terminals of the semiconductor device 4 to each other are formed on the surface of the substrate 101. The reason why the electrode pads on which the conductive bumps 5, 6 are placed are separate from the through-hole electrodes is that the conductive bumps such as solder bumps or the like are prevented from being absorbed in the through-holes.
The through-hole electrode pads B111 to B134 and C111 to C134 of FIGS. 12A and 12B are electrically connected to the through-hole electrode pads B111' to B134' and C111' to C134' (only reference numerals, not shown) formed on the back of the substrates 100 and 101 through through-holes. The same electrode pads 111' to 134' and 141' to 164' (only reference numerals, not shown) are formed on the back side of the substrates 100 and 101 of the electrode pads 111 to 134 and 141 to 164.
The electrode pads 111' to 134' on the back side of the substrate 100 are respectively connected to the through-hole electrode pads B111' to B134' on the same back side, and the electrode pads 141' to 164' of the back side of the substrate 101 are respectively connected to the through-hole electrode pads C111' to C134' on the back side.
Thus, the electrode pads and the through-hole electrodes are formed in pair on the surface side and back side of the substrates 100, 101, whereby the electrode patterns are made uniform so as to improve productivity in pattern printing.
The conductive bumps 6 directly connect the electrode pads 141 to 164 on the surface side of the lower substrate 101 and the electrode pads 111' to 134' on the back side of the upper substrate 100 to each other. The condition of the connection is shown in FIGS. 13 and 14.
FIGS. 13 is a perspective view of a J-part of FIG. 11 to an enlarged scale, and FIG. 14 is a sectional view taken along line G--G of FIG. 11. As shown in FIGS. 13 and 14, the through electrode pads B111 and B111', B112 and B112', C111 and C111', C112 and C112' are respectively connected to each other by through-hole internal electrodes S31, S32, S33, S34. The conductive bumps 6, as shown in FIG. 13, directly connect the electrode pads 111', 112' on the back side of the upper substrate 100 to the electrode pads 141, 142 on the surface side of the lower substrate 101 to each other. The connection form of the other electrode pad part is also similar to FIGS. 13 and 14. As the result, the respective electrode pads of the substrates 100, 101 are directly connected to each other vertically through the conductive bumps 6.
As described above, the semiconductor devices 3 and 4 are vertically direct-coupled to each other through the conductive bumps 6 to be connected, and mounted facedown on a motherboard not shown through the conductive bumps 5.
Again in FIGS. 12A and 12B, connection for chip select is a wiring part between the RAS terminal of the semiconductor chip 3 and the electrode pads 111, 112, and between the RAS terminal of the semiconductor chip 4 and the electrode pads 141, 142 (through hole electrode pads B111, B112, C111, C112). However, the connection pattern for chip select differs with the substrates of the respective layers.
In the case of selecting the semiconductor chip 3 at the time of reading and writing data, as shown in FIG. 12A, a chip select signal is supplied to the electrode pad connected to the RAS of the semiconductor chip 3. At this time, the chip select signal is transmitted to the electrode pad 142, but this is not connected to the RAS, so that the semiconductor device 4 is not selected. On the other hand, in the case of selecting the semiconductor chip 4 at the time of reading and writing, a chip select signal is supplied to the electrode pad 111 connected to the RAS of the semiconductor chip 4. Thus, selection from the semiconductor devices 3 and 4 is enabled by supplying a chip select signal one of the electrode pads 111, 112 of the substrate 100.
In the described conventional stacked module, chip select is enabled by changing wiring for chip select at every stage of the substrates. Hence it is necessary to use different substrates in the respective layers in the stacked module.
That is, it is necessary to manufacture substrates with plural wiring patterns, so that productivity is low and the yield is bad. Further, when the arrangement of substrates in the stacked module is wrong, it is necessary to replace the whole of the stacked module.